This invention relates to dry etching technologies used in a process for fabricating semiconductor devices and, more particularly, to a dry etching system and a method of dry etching.
Various kinds of dry etching systems have been proposed for transferring a photo-resist etching mask to semiconductor wafers. These dry etching systems are broken down into two categories. The first category is featured by concurrently treating a lot of semiconductor wafers with etching gas. On the other hand, only one semiconductor wafer is treated with etching gas in the dry etching system of the second category. The dry etching in the first category is a kind of batch process, and the dry etching in the second category is called as a single wafer processing. Although a high throughput is achieved by the dry etching system of the first category, it is difficult to uniformly etch the material on the plural semiconductor wafers. On the other hand, the dry etching system of the second category is lower in the throughput than the dry etching system of the first category: However, the etching is well controlled on the single semiconductor wafer. For this reason, when a semiconductor manufacturer is to form micro-contact holes in material layers on plural semiconductor wafers, the semiconductor manufacturer usually employs the dry etching system of the second category for the micro-contact holes, because the uniformity is the important factor in the formation of the micro-contact holes among the plural semiconductor wafers.
A typical example of the dry etching system of the second category has an upper electrode and an electrostatic stage in the etching chamber. Plural gas outlet holes are formed in the upper electrode, and a gas supply system is connected to the plural gas outlet holes. The electrostatic stage is opposed to the upper electrode, and a single semiconductor wafer is to be electrostatically fixed to the upper surface of the electrostatic stage.
Micro-contact holes are formed in an insulating layer over a single semiconductor wafer as follows. First, photo-resist solution is spun onto the single semiconductor wafer, and is baked so as to form a photo-resist layer on the insulating layer. A pattern image for the micro-contact holes is optically transferred from a photo-mask to the photo-resist layer, and a latent image is produced in the photo-resist layer. When the latent image is developed, a photo-resist etching mask is left on the insulating layer. Predetermined surface areas of the insulating layer are exposed to the holes formed in the photo-resist etching mask, and the micro-contact holes are to be opened to the predetermined surface areas.
The single semiconductor wafer is conveyed into the etching chamber, and is placed on the electrostatic stage. Direct current voltage or electrostatic charge voltage is applied thereto. Then, the single semiconductor wafer is electrostatically attracted to the electrostatic stage. Vacuum is developed in the etching chamber, and the etching chamber is maintained at predetermined vacuum. Process gas is introduced into the etching chamber, and high-frequency electric power is applied between the upper electrode and the lower electrode. Then, plasma is created, and the predetermined surface areas are subjected to the ion-bombardment. However, the remaining surface area is covered with the photo-resist etching mask, and is free from the ion-bombardment. As a result, the insulating layer is partially etched away, and the micro-contact holes are formed in the insulating layer.
However, a problem is encountered in the prior art dry etching method carried out in the dry etching system of the second category in poor reproducibility of the micro-contact holes. FIG. 1 shows an experiment carried out by the present inventor. The present inventor formed the photo-resist etching masks for the micro-contact holes over semiconductor wafers, and the photo-resist etching masks had the same pattern for the micro-contact holes. The micro-contact holes were formed through the prior art dry etching in order, and the present inventor measured the diameter of the micro-contact holes. The micro-contact holes of the first semiconductor wafer had the diameter greater than L7. The micro-contact holes of the second semiconductor wafer had the diameter between L6 and L7. The micro-contact holes of the third semiconductor wafer had the diameter greater than that of the second semiconductor wafer. The diameter of the micro-contact holes of the fourth/fifth semiconductor wafers were approximately equal to that of the third semiconductor wafer. Thus, the prior art dry etching resulted in that the micro-contact holes got small after the initial stage. This tendency was serious if the prior art dry etching system remained stopping for a long time period.
There are several reasons for the poor reproducibility. One of the reasons is low temperature at the initial stage of the prior art dry etching due to poor electrostatic attraction between the electrostatic stage and the semiconductor wafer. When the dry etching is carried out in the low temperature, the ion-bombardment tends to be concentrated to the periphery of the semiconductor wafer, and enlarge the micro-contact holes in the periphery of the semiconductor wafer.
In order to enhance the reproducibility of the micro-contact holes, dummy wafers are used in the initial stage when the temperature is rising. When the temperature gets stable, the dummy wafer is changed to a semiconductor wafer, and the micro-contact holes are formed on the semiconductor wafer. However, the dummy wafers result in a low throughput, and the solution is not desirable.
Another solution is disclosed in Japanese Patent Publication of Unexamined Application (laid-open) No. 6-170670. According to the Japanese Patent Publication of Unexamined Application, the dry etching system disclosed therein is equipped with a static chuck on the lower electrode. A pressure sensor and a temperature sensor are provided for the static chuck. The pressure sensor is embedded in the static chuck, and the electrostatic attraction between the semiconductor wafer and the static chuck is monitored by the pressure sensor. While the dry etching is being carried out in the plasma, the pressure sensor and the temperature sensor report the actual pressure and the actual temperature to a controller. When the controller is noticed that the etching condition is varied, the static chuck changes the electrostatic attraction to the semiconductor wafer and/or the temperature is varied. The reproducibility is a little bit improved in the prior art dry etching system disclosed in the Japanese Patent Publication of Unexamined Application. However, the effect is not drastic. This is because of the fact that the pressure sensor is less reliable in high the temperature ambience under the ion-bombardment. This means that the static chuck changes the electrostatic attraction on the basis of inaccurate detection.
It is therefore an important object of the present invention to provide a dry etching system, which achieves good reproducibility without sacrifice of the throughput.
It is also an important object of the present invention to provide a dry etching method, which is used in the dry etching system.
The present inventor contemplated the problem inherent in the prior art dry etching. The present inventor investigated the influence of the direct current voltage or the electric static charge applied to the static chuck on the contact holes. The present inventor formed photo-resist etching masks on layers deposited over semiconductor wafers, respectively. The photo-resist etching masks had a pattern for micro-contact holes to be formed in the central areas of the layers as well as micro-contact holes to be formed in the peripheral areas of the layers. The present inventor carried out the dry etching under the direct current voltage varied together with the semiconductor wafers. The present inventor measured the diameter of the micro-contact holes formed in the layers on the semiconductor wafers. The values of the diameter were plotted in FIG. 2 in terms of the direct current voltage. The direct current voltage is abbreviated as xe2x80x9cESCxe2x80x9d voltage in FIG. 2.
The present inventor firstly noticed that the direct current voltage was less influential on the micro-contact holes formed in the central areas of the layers. Another discovery was that the diameter of the micro-contact holes was decreased in reverse to the direct current voltage ESC.
The present inventor investigated the different tendencies, and supposed that helium to transfer the heat between the central area and the peripheral area insufficiently. In detail, a heater was provided in the static chuck, and helium gas flew into between the static chuck and the back surface of the semiconductor wafer. The helium gas was expected to eliminate a temperature difference between the central area and the peripheral area, if any, by carrying the heat from the low temperature area to the high temperature area. If the helium gas was perfectly sealed, the helium gas served as a heat carrier, and made the temperature uniform over the back surface of the semiconductor wafer. This resulted in the chemical reaction uniformly between the central area and the peripheral area regardless of the electrostatic attraction between the static chuck and the semiconductor wafer. However, the chemical reaction was unstable in the peripheral area rather than in the central area. The present inventor doubted that the helium gas was hermetically sealed between the static chuck and the semiconductor wafer, because the chemical reaction was varied together with the electrostatic attraction.
The present inventor installed a helium gas detector around the semiconductor wafer on the static chuck, and checks the helium gas detector to see whether or not the helium gas was leaked and whether or not the amount of leakage helium gas was varied with the electrostatic attraction between the static chuck and the semiconductor wafer. The detection proved the doubt to be correct.
In accordance with one aspect of the present invention, there is provided a dry etching system comprising a reactor having an etching chamber therein, a static chuck provided in the etching chamber and supplied with a direct current voltage so as to electrostatically attracting a single semiconductor wafer thereto, a gas control system supplying a process gas to the etching chamber and maintaining the pressure of the process gas at a target range, a plasma generator provided in the etching chamber and generating a plasma from the process gas in the vicinity of the single semiconductor wafer for a dry etching, and a process controlling system for supervising the dry etching and changing the direct current voltage between a standard value and a certain value different from the standard value on the basis of a place occupied by the single semiconductor wafer in a semiconductor wafer lot and a lapse of time from the previous dry etching.
In accordance with another aspect of the present invention, there is provided a method for a dry etching comprising the steps of a) conveying a single semiconductor wafer from a semiconductor wafer lot onto a static chuck, b) determining a magnitude of a direct current voltage to be applied to the static chuck on the basis of a place occupied by the single semiconductor wafer in the semiconductor wafer lot and a lapse of time from the previous dry etching, c) getting ready for the dry etching through application of the direct current voltage to the static chuck for electrostatically attracting the single semiconductor wafer to the static chuck, and d) carrying out the dry etching on the single semiconductor wafer.